Concurrently optimized system-on-chip implementation with automatic synthesis and integration
US10031992B2 · kind B2 · utility
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18Claims
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Key dates
| Filing date | Dec 23, 2016 |
| Grant date | Jul 24, 2018 |
| Priority date | — |
| Expiry date | Dec 23, 2036 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2119/18
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A computer-implemented method for manufacturing an integrated circuit (IC) chip includes defining digital block specifications for the IC; and automatically synthesizing and integrating digital blocks with support circuits in accordance with the digital block specifications.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.