Semiconductor package and manufacturing method thereof
US10032705B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 8, 2016 |
| Grant date | Jul 24, 2018 |
| Priority date | — |
| Expiry date | May 8, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/19106
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor package and a method of manufacturing a semiconductor package. As a non-limiting example, various aspects of this disclosure provide a semiconductor package, and method of manufacturing thereof, that comprises a substrate having a first surface and a second surface opposite to the first surface, and comprising at least one first recess portion formed in a direction ranging from the first surface toward the second surface, a plurality of first recess conductive patterns formed in the first recess portion, and a first passive element inserted into the first recess portion of the substrate and having a first electrode and a second electrode electrically connected to the plurality of first recess conductive patterns.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.