Patent · US Active

Power semiconductor arrangement having a plurality of power semiconductor switching elements and reduced inductance asymmetry

US10032755B2 · kind B2 · utility

1Cited by

1References

17Claims

0Family size

Assignee

Infineon Technologies AG · DE

Inventors

Daniel Domes · Schwäbisch Hall, DE
Reinhold Bayerer · Warstein, DE
Waleri Brekel · Erwitte, DE

Key dates

Filing date	Nov 8, 2016
Grant date	Jul 24, 2018
Priority date	—
Expiry date	Nov 8, 2036

Classification

Technology area (CPC H)Electricity
CPC primaryH01L2924/3011
WIPO fieldSemiconductors
WIPO sectorElectrical engineering

Abstract

A multiplicity of power semiconductor switching elements of the same type parallel have a load current terminal for a load current input and a load current terminal for a load current output. At least one outer load current terminal and at least one inner load current terminal per load current direction include a load current input and a load current output. At least one contacting device for common electrical contacting all of the load current terminals of the same load current direction includes a load current input and a load current output. The contacting device includes a plurality of terminal tongues which are respectively fastened on an associated load current terminal. The geometry and/or profile of the terminal tongue of an outer load current terminal differs from the geometry and/or profile of the terminal tongue of an inner load current terminal of the same contacting device.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.