Circuit for and method of measuring latency in an integrated circuit
US10033523B1 · kind B1 · utility
4Cited by
16References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Aug 14, 2017 |
| Grant date | Jul 24, 2018 |
| Priority date | — |
| Expiry date | Aug 14, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L7/048
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A circuit for measuring latency in an integrated circuit device is described. The circuit comprises a transmitter circuit having signal generator configured to generate a test signal having a marker for determining a latency in a path associated with the integrated circuit device; and a latency calculation circuit coupled to the signal generator and having a latency adjustment circuit and a unit interval (UI) adjustment circuit; wherein the latency calculation circuit generates a latency value (LATENCY) based upon a latency count from the latency adjustment circuit and a UI adjustment from the UI adjustment circuit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.