Inventor · Redwood City, CA, US

Warren E. Cory

22Patents
12h-index
18Co-inventors
78Inventor score

Filing activity: Feb 22, 2002 → Mar 31, 2023

Most-cited inventions

PatentTitleAreaCited byStatus
US6617877B1 Variable data width operation in multi-gigabit transceivers on a programmable logic device Electricity 46 Expired
US7519747B1 Variable latency buffer and method of operation Physics 34 Active
US6970013B1 Variable data width converter Physics 28 Expired
US7295639B1 Distributed adaptive channel bonding control for improved tolerance of inter-channel skew Physics 22 Expired
US7623660B1 Method and system for pipelined decryption Electricity 21 Active
US8245102B1 Error checking parity and syndrome of a block of data with relocated parity bits Electricity 20 Active
US7099426B1 Flexible channel bonding and clock correction operations on a multi-block data path Physics 19 Expired
US8411703B1 Method and apparatus for a reduced lane-lane skew, low-latency transmission system Electricity 17 Active
US7913104B1 Method and apparatus for receive channel data alignment with minimized latency variation Electricity 17 Active
US7426678B1 Error checking parity and syndrome of a block of data with relocated parity bits Electricity 13 Active
US10528513B1 Circuit for and method of providing a programmable connector of an integrated circuit device Physics 12 Active
US7187709B1 High speed configurable transceiver architecture Physics 12 Expired
US7382823B1 Channel bonding control logic architecture Electricity 8 Expired
US7111220B1 Network physical layer with embedded multi-standard CRC generator Electricity 7 Expired
US10038450B1 Circuits for and methods of transmitting data in an integrated circuit Electricity 7 Active
US7088767B1 Method and apparatus for operating a transceiver in different data rates Physics 6 Expired
US10623174B1 Low latency data transfer technique for mesochronous divided clocks Electricity 6 Active
US6960933B1 Variable data width operation in multi-gigabit transceivers on a programmable logic device Electricity 4 Expired
US10033523B1 Circuit for and method of measuring latency in an integrated circuit Electricity 4 Active
US7895509B1 Error checking parity and syndrome of a block of data with relocated parity bits Electricity 3 Active
US8301988B1 Error checking parity and syndrome of a block of data with relocated parity bits Electricity 1 Active
US12248761B2 Deterministic reset mechanism for asynchronous gearbox FIFOs for predictable latency Physics 0 Active

Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.