Variable gate width for gate all-around transistors

US10038054B2 · kind B2 · utility

Assignee

• Intel Corporation · US

Inventors

• Willy Rachmady · Beaverton, US
• Van H. Le · Portland, US
• Ravi Pillarisetty · Portland, US
• Jack T. Kavalieros · Portland, US
• Robert S. Chau · Beaverton, US
• Seung Hoon Sung · Beaverton, US

Key dates

• Filing date: Feb 9, 2017
• Grant date: Jul 31, 2018
• Expiry date: Feb 9, 2037

Classification

• Technology area (CPC Y): Emerging Cross-Sectional Technologies
• CPC primary: Y10S977/938
• WIPO field: Micro-structural and nano-technology
• WIPO sector: Chemistry

Abstract

Nanowire-based gate all-around transistor devices having one or more active nanowires and one or more inactive nanowires are described herein. Methods to fabricate such devices are also described. One or more embodiments of the present invention are directed at approaches for varying the gate width of a transistor structure comprising a nanowire stack having a distinct number of nanowires. The approaches include rendering a certain number of nanowires inactive (i.e. so that current does not flow through the nanowire), by severing the channel region, burying the source and drain regions, or both. Overall, the gate width of nanowire-based structures having a plurality of nanowires may be varied by rendering a certain number of nanowires inactive, while maintaining other nanowires as active.