Inventor · Portland, OR, US

Van H. Le

251Patents
11h-index
158Co-inventors
79Inventor score

Filing activity: Sep 24, 2010 → Feb 16, 2024

Most-cited inventions

PatentTitleAreaCited byStatus
US9123567B2 CMOS implementation of germanium and III-V nanowires and nanoribbons in gate-all-around architecture Electricity 57 Active
US8987794B2 Non-planar gate all-around device and method of fabrication thereof Electricity 54 Active
US8765563B2 Trench confined epitaxially grown device layer(s) Electricity 34 Active
US8748940B1 Semiconductor devices with germanium-rich active layers and doped transition layers Emerging Cross-Sectional Technologies 28 Active
US9123790B2 Contact techniques and configurations for reducing parasitic resistance in nanowire transistors Emerging Cross-Sectional Technologies 20 Active
US10763349B2 Quantum dot devices with modulation doped stacks Electricity 18 Active
US8575653B2 Non-planar quantum well device having interfacial layer and method of forming same Electricity 17 Active
US9590089B2 Variable gate width for gate all-around transistors Emerging Cross-Sectional Technologies 14 Active
US8785907B2 Epitaxial film growth on patterned substrate Electricity 12 Active
US9634007B2 Trench confined epitaxially grown device layer(s) Electricity 12 Active
US9570614B2 Ge and III-V channel semiconductor devices having maximized compliance and free surface relaxation Electricity 11 Active
US9472613B2 Conversion of strain-inducing buffer to electrical insulator Electricity 11 Active
US8872225B2 Defect transferred and lattice mismatched epitaxial film Electricity 10 Active
US9391181B2 Lattice mismatched hetero-epitaxial film Electricity 9 Active
US9129827B2 Conversion of strain-inducing buffer to electrical insulator Electricity 9 Active
US9029835B2 Epitaxial film on nanoscale structure Electricity 9 Active
US10038054B2 Variable gate width for gate all-around transistors Emerging Cross-Sectional Technologies 9 Active
US9136343B2 Deep gate-all-around semiconductor device having germanium or group III-V active layer Electricity 9 Active
US8710490B2 Semiconductor device having germanium active layer with underlying parasitic leakage barrier layer Electricity 8 Active
US9337291B2 Deep gate-all-around semiconductor device having germanium or group III-V active layer Electricity 8 Active
US9691843B2 Common-substrate semiconductor devices having nanowires or semiconductor bodies with differing material orientation or composition Electricity 7 Active
US11171243B2 Transistor structures with a metal oxide contact buffer Electricity 7 Active
US10096709B2 Aspect ratio trapping (ART) for fabricating vertical semiconductor devices Electricity 6 Active
US10418487B2 Non-planar gate all-around device and method of fabrication thereof Electricity 6 Active
US10693008B2 Cladding layer epitaxy via template engineering for heterogeneous integration on silicon Electricity 6 Active

Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.