Three-level ferroelectric memory cell using band alignment engineering
US10038092B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | May 24, 2017 |
| Grant date | Jul 31, 2018 |
| Priority date | — |
| Expiry date | May 24, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/0415
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A non-volatile memory cell stores 1.5 bits of data in three polarization states. The memory cell may have two ferroelectric layers and three electrodes. The energy bands of the ferroelectric layers are adjusted by providing two of the electrodes with different work functions. The difference in the work functions may be significant, such as at least 0.4-0.6 V or more. Two of the electrodes may have equal or similar work functions. For example, the work functions may be equal within a tolerance of +/−0.1 V. The memory cell can be arranged in various configurations including a FeFET (ferroelectric field effect transistor) and a FeRAM (ferroelectric random access memory). A set of memory cells can be arranged in a string such as a NAND string.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.