VSS bitcell sleep scheme involving modified bitcell for terminating sleep regions
US10043572B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 28, 2017 |
| Grant date | Aug 7, 2018 |
| Priority date | — |
| Expiry date | Jul 28, 2037 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/418
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A system and method for providing efficient power, performance and stability tradeoffs of memory accesses are described. A computing system uses a memory for storing data, and a processing unit, which generates access request. The memory stores data and includes a dummy cell between a first region and a second region. The first region and the second region operate with at least one of two operating states such as an awake state and a sleep state. The dummy cell uses two ground connections to support two separate ground references. In one example, a first ground reference is zero volts and a second ground reference is a floating node. In another example, the first ground reference is a value shared by one of the two regions and the second ground reference is the floating node.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.