Vertically integrated nanosheet fuse
US10043748B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 13, 2017 |
| Grant date | Aug 7, 2018 |
| Priority date | — |
| Expiry date | Nov 13, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/679
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Embodiments are directed to a method and resulting structures for forming a semiconductor device having a vertically integrated nanosheet fuse. A nanosheet stack is formed on a substrate. The nanosheet stack includes a semiconductor layer formed between an upper nanosheet and a lower nanosheet. The semiconductor layer is modified such that an etch rate of the modified semiconductor layer is greater than an etch rate of the upper and lower nanosheets when exposed to an etchant. Portions of the modified semiconductor layer are removed to form a cavity between the upper and lower nanosheets and a silicide region is formed in the upper nanosheet.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.