Semiconductor device and method for fabricating the same
US10043809B1 · kind B1 · utility
Assignees
Inventors
Key dates
| Filing date | Jun 26, 2017 |
| Grant date | Aug 7, 2018 |
| Priority date | — |
| Expiry date | Jun 26, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B12/50
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for fabricating semiconductor device includes the steps of: providing a substrate having a cell region and a peripheral region; forming a bit line structure on the cell region and a gate structure on the peripheral region; forming an interlayer dielectric (ILD) layer around the bit line structure and the gate structure; forming a conductive layer on the bit line structure; performing a first photo-etching process to remove part of the conductive layer for forming storage contacts adjacent two sides of the bit line structure and contact plugs adjacent to two sides of the gate structure; forming a first cap layer on the cell region and the peripheral region to cover the bit line structure and the gate structure; and performing a second photo-etching process to remove part of the first cap layer on the cell region.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.