Semiconductor structure for preventing row hammering issue in DRAM cell and method for manufacturing the same
US10043811B1 · kind B1 · utility
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Key dates
| Filing date | Jun 20, 2017 |
| Grant date | Aug 7, 2018 |
| Priority date | — |
| Expiry date | Jun 20, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B12/34
Abstract
A semiconductor structure for preventing row hammering issue in DRAM cell is provided in the present invention. The structure includes a trench with a gate dielectric, an n-type work function metal layer, a TiN layer conformally formed within, and a buried word line filled in the trench.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.