Post gate silicon germanium channel condensation and method for producing the same
US10043893B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 3, 2017 |
| Grant date | Aug 7, 2018 |
| Priority date | — |
| Expiry date | Aug 3, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D86/215
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Methods of forming a graded SiGe percentage PFET channel in a FinFET or FDSOI device by post gate thermal condensation and oxidation of a high Ge percentage channel layer and the resulting devices are provided. Embodiments include forming a gate dielectric layer over a plurality of Si fins formed over a substrate; forming a gate over each fin; forming a HM and spacer layer over and on sidewalls of each gate; forming a u-shaped cavity in each fin adjacent to the gate and spacer layer; epitaxially growing an un-doped high percentage SiGe layer in each u-shaped cavity and along sidewalls of each fin; thermally condensing the high percentage SiGe layer, an un-doped low percentage SiGe formed underneath in the substrate and fins; and forming a S/D region over the high percentage SiGe layer in each u-shaped cavity, an upper surface of the S/D regions below the gate dielectric layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.