Thermoelectric cooling using through-silicon vias
US10043962B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 5, 2016 |
| Grant date | Aug 7, 2018 |
| Priority date | — |
| Expiry date | Aug 20, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10N10/01
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Structures that include thermoelectric couples and methods for fabricating such structures. A device level and a back-end-of-line (BEOL) interconnect structure are fabricated at a front side of a substrate. A thermoelectric couple is formed that is coupled with the substrate. The thermoelectric couple includes a first through-silicon via extending through the device level and the substrate to a back side of the substrate, a second through-silicon via extending through the device level and the substrate to the back side of the substrate, an n-type thermoelectric pillar coupled with the first through-silicon via, and a p-type thermoelectric pillar coupled with the second through-silicon via. The BEOL interconnect structure includes a wire that couples the first through-silicon via in series with the second through-silicon via.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.