Methodology for pattern density optimization
US10049178B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 1, 2016 |
| Grant date | Aug 14, 2018 |
| Priority date | — |
| Expiry date | Jun 1, 2036 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG03F1/36
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The present disclosure relates to a method of improving pattern density with a low OPC (optical proximity correction) cycle time, and an associated apparatus. In some embodiments, the method is performed by performing an initial data preparation process on an IC design including a graphical representation of a layout used to fabricate an integrated chip. The initial data preparation process is performed by using a data preparation element to generate a modified IC design having modified shapes that are modified forms of shapes within the IC design. One or more low-pattern-density areas of the modified IC design are identified using a local density checking element. One or more dummy shapes are added within the one or more low-pattern-density areas using a dummy shape insertion element. The one or more dummy shapes are separated from the modified shapes by a non-zero space.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.