Method of manufacturing a semiconductor device having a vertical edge termination structure
US10049912B2 · kind B2 · utility
0Cited by
11References
15Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Feb 3, 2017 |
| Grant date | Aug 14, 2018 |
| Priority date | — |
| Expiry date | Feb 3, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/256
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of manufacturing a semiconductor device includes forming a frame trench extending from a first surface into a base substrate, forming, in the frame trench, an edge termination structure comprising a glass structure, forming a conductive layer on the semiconductor substrate and the edge termination structure, and removing a portion of the conductive layer above the edge termination structure. A remnant portion of the conductive layer forms a conductive structure that covers a portion of the edge termination structure directly adjoining a sidewall of the frame trench.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.