Methods for SiO2 filling of fine recessed features and selective SiO2 deposition on catalytic surfaces
US10049913B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Apr 11, 2017 |
| Grant date | Aug 14, 2018 |
| Priority date | — |
| Expiry date | Apr 11, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/02304
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Methods for void-free SiO2 filling of fine recessed features and selective SiO2 deposition on catalytic surfaces are described. According to one embodiment, the method includes providing a substrate containing recessed features, coating surfaces of the recessed features with a metal-containing catalyst layer, in the absence of any oxidizing and hydrolyzing agent, exposing the substrate at a substrate temperature of approximately 150° C. or less, to a process gas containing a silanol gas to deposit a conformal SiO2 film in the recessed features, and repeating the coating and exposing at least once to increase the thickness of the conformal SiO2 film until the recessed features are filled with SiO2 material that is void-free and seamless in the recessed features. In one example, the recessed features filled with SiO2 material form shallow trench isolation (STI) structures in a semiconductor device.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.