Method of manufacturing selective nanostructures into finFET process flow
US10049944B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 5, 2016 |
| Grant date | Aug 14, 2018 |
| Priority date | — |
| Expiry date | Oct 5, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/018
Abstract
A method for integrating nanostructures in finFET processing and a related device are provided. Embodiments include forming fins in a Si substrate in first and second device regions; forming STI regions in spaces between fins; forming a first hardmask over the fins and STI regions; removing a portion of the first hardmask over the first device region to expose upper surfaces of the fins and STI regions in the first device region; recessing an upper portion of the fins; forming first devices over the recessed fins; forming a second hardmask over the fins and STI regions; removing a portion of the second hardmask over the second device region to expose upper surfaces of the fins and STI regions; recessing an upper portion of the fins; and forming second devices, different from the first devices, over the recessed fins, wherein the first and/or second devices include nanowire or nanosheet devices.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.