Scott Beasor
33Patents
5h-index
61Co-inventors
64Inventor score
Filing activity: May 20, 2013 → Jan 30, 2020
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US9812453B1 | Self-aligned sacrificial epitaxial capping for trench silicide | Electricity | 17 | Active |
| US10373877B1 | Methods of forming source/drain contact structures on integrated circuit products | Electricity | 8 | Active |
| US9397004B2 | Methods for fabricating FinFET integrated circuits with simultaneous formation of local contact openings | Electricity | 8 | Active |
| US10326002B1 | Self-aligned gate contact and cross-coupling contact formation | Electricity | 6 | Active |
| US9330971B2 | Method for fabricating integrated circuits including contacts for metal resistors | Electricity | 6 | Active |
| US9419082B2 | Source/drain profile engineering for enhanced p-MOSFET | Electricity | 4 | Active |
| US10049944B2 | Method of manufacturing selective nanostructures into finFET process flow | Electricity | 3 | Active |
| US10586736B2 | Hybrid fin cut with improved fin profiles | Electricity | 3 | Active |
| US9984933B1 | Silicon liner for STI CMP stop in FinFET | Electricity | 3 | Active |
| US10043708B2 | Structure and method for capping cobalt contacts | Electricity | 2 | Active |
| US10879180B2 | FinFET with etch-selective spacer and self-aligned contact capping layer | Electricity | 2 | Active |
| US10361289B1 | Gate oxide formation through hybrid methods of thermal and deposition processes and method for producing the same | Electricity | 1 | Active |
| US10403742B2 | Field-effect transistors with fins formed by a damascene-like process | Electricity | 1 | Active |
| US10629739B2 | Methods of forming spacers adjacent gate structures of a transistor device | Electricity | 1 | Active |
| US10832966B2 | Methods and structures for a gate cut | Electricity | 1 | Active |
| US10475890B2 | Scaled memory structures or other logic devices with middle of the line cuts | Electricity | 1 | Active |
| US10580701B1 | Methods of making a self-aligned gate contact structure and source/drain metallization structures on integrated circuit products | Electricity | 1 | Active |
| US10707175B2 | Asymmetric overlay mark for overlay measurement | Electricity | 1 | Active |
| US10818659B2 | FinFET having upper spacers adjacent gate and source/drain contacts | Electricity | 1 | Active |
| US10872979B2 | Spacer structures for a transistor device | Electricity | 1 | Active |
| US10832965B2 | Fin reveal forming STI regions having convex shape between fins | Electricity | 1 | Active |
| US10763176B2 | Transistor with a gate structure comprising a tapered upper surface | Electricity | 0 | Active |
| US10804379B2 | FinFET device and method of manufacturing | Electricity | 0 | Active |
| US10636890B2 | Chamfered replacement gate structures | Electricity | 0 | Active |
| US10797049B2 | FinFET structure with dielectric bar containing gate to reduce effective capacitance, and method of forming same | Electricity | 0 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.