Arrangement of multiple power semiconductor chips and method of manufacturing the same

US10049962B2 · kind B2 · utility

Assignee

• Infineon Technologies AG · DE

Inventors

• Georg Meyer-Berg · Birkenfeld, DE
• Edward Fuergut · Nuremberg, DE
• Joachim Mahler · Regensburg, DE

Key dates

• Filing date: Jun 2, 2016
• Grant date: Aug 14, 2018
• Expiry date: Jun 2, 2036

Classification

• Technology area (CPC H): Electricity
• CPC primary: H05K7/20
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

A semiconductor power arrangement includes a chip carrier having a first surface and a second surface opposite the first surface. The semiconductor power arrangement further includes a plurality of power semiconductor chips attached to the chip carrier, wherein the power semiconductor chips are inclined to the first and/or second surface of the chip carrier.