Low resistance seed enhancement spacers for voidless interconnect structures
US10049980B1 · kind B1 · utility
6Cited by
10References
16Claims
0Family size
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Key dates
| Filing date | Feb 10, 2017 |
| Grant date | Aug 14, 2018 |
| Priority date | — |
| Expiry date | Feb 10, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L23/53238
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An interconnect structure is provided in which a seed enhancement spacer is present on vertical surfaces, but not a horizontal surface, of a diffusion barrier liner that is located in an opening present in an interconnect dielectric material layer. An interconnect metal or metal alloy structure is present on physically exposed sidewalls of the seed enhancement spacer and on the physically exposed horizontal surface of the diffusion barrier liner.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.