Method for late differential SOI thinning for improved FDSOI performance and HCI optimization

US10050119B2 · kind B2 · utility

Assignee

• GlobalFoundries Inc. · KY

Inventors

• George R. Mulfinger · Gansevoort, US
• Dina H. Triyoso · Mechanicville, US
• Ryan Sporer · Mechanicville, US

Key dates

• Filing date: Sep 2, 2016
• Grant date: Aug 14, 2018
• Expiry date: Sep 2, 2036

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D30/0275

Abstract

Methods for selectively thinning a silicon channel area under a gate electrode and resulting devices are disclosed. Embodiments include providing a SOI substrate including a Si-layer; providing a first dummy-gate electrode over a first gate-oxide between first spacers over a first channel area of the Si-layer and a second dummy-gate electrode over a second gate-oxide between second spacers over a second channel area of the Si-layer; forming a S/D region adjacent each spacer; forming an oxide over the S/D regions and the spacers; removing the dummy-gate electrodes creating first and second cavities between respective first and second spacers; forming a mask with an opening over the first cavity; removing the first gate-oxide; thinning the Si-layer under the first cavity, forming a recess in the Si-layer; forming a third gate-oxide on recess side and bottom surfaces; and filling the recess and the cavities with metal, forming first and second RMG electrodes.