High performance memory controller
US10055293B2 · kind B2 · utility
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9Claims
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Key dates
| Filing date | May 1, 2017 |
| Grant date | Aug 21, 2018 |
| Priority date | — |
| Expiry date | May 1, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M13/45
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory device includes a memory array that includes a buffer data. The memory device also includes a memory controller. The memory controller includes an error correction code (ECC) component. The memory controller further receives a status command and an indication related to the quality of the data to analyze with the ECC component. Based on a status value, the memory controller utilizes one of a plurality of error correction techniques via the ECC component to correct an error (e.g., soft state, calibration, etc.).
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.