Inventor · Avezzano, IT

Walter Di Francesco

38Patents
3h-index
72Co-inventors
62Inventor score

Filing activity: May 5, 2008 → May 23, 2024

Most-cited inventions

PatentTitleAreaCited byStatus
US11177014B1 Global-local read calibration Physics 7 Active
US7848158B2 Methods and apparatuses for programming flash memory using modulated pulses Physics 6 Active
US9076547B2 Level compensation in multilevel memory Physics 4 Active
US10593412B2 Using a status indicator in a memory sub-system to detect an event Physics 3 Active
US10854305B2 Using a status indicator in a memory sub-system to detect an event Physics 1 Active
US11908523B2 Express programming using advanced cache register release in a memory sub-system Physics 1 Active
US11416154B2 Partially written block treatment Physics 1 Active
US10423350B2 Partially written block treatment Physics 1 Active
US9620236B2 Level compensation in multilevel memory Physics 1 Active
US12340851B2 Memories for performing successive programming operations Physics 0 Active
US9639420B2 High performance memory controller Electricity 0 Active
US11842078B2 Asynchronous interrupt event handling in multi-plane memory devices Physics 0 Active
US11977748B2 Prioritized power budget arbitration for multiple concurrent memory access operations Emerging Cross-Sectional Technologies 0 Active
US12393249B2 Peak power management with data window reservation Emerging Cross-Sectional Technologies 0 Active
US12327595B2 Shortened single-level cell memory programming Physics 0 Active
US12205653B2 Wordline or pillar state detection for faster read access times Physics 0 Active
US12001336B2 Hybrid parallel programming of single-level cell memory Physics 0 Active
US12183407B2 Setting switching for single-level cells Physics 0 Active
US12068034B2 Two-pass corrective programming for memory cells that store multiple bits and power loss management for two-pass corrective programming Physics 0 Active
US10877679B2 Partially written block treatment Physics 0 Active
US12393526B2 NAND page buffer based security operations Physics 0 Active
US12189949B2 Bit error management in memory devices Physics 0 Active
US11636908B2 Global-local read calibration Physics 0 Active
US10055293B2 High performance memory controller Electricity 0 Active
US12007912B2 NAND page buffer based security operations Physics 0 Active

Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.