Patent · US Active

Non-disruptive clearing of varying address ranges from cache

US10055355B1 · kind B1 · utility

1Cited by

6References

1Claims

0Family size

Assignee

International Business Machines Corporation · US

Inventors

Ekaterina M. Ambroladze · Los Angeles, US
Deanna Postles Dunn Berger · Poughkeepsie, US
Michael A. Blake · Wappingers Falls, US
Pak-kin Mak · Poughkeepsie, US
Robert J. Sonnelitter, III · Wappingers Falls, US
Guy G. Tracy · Austin, US
Chad G. Wilson · Palo Alto, US

Key dates

Filing date	Sep 27, 2017
Grant date	Aug 21, 2018
Priority date	—
Expiry date	Sep 27, 2037

Classification

Technology area (CPC G)Physics
CPC primaryG06F2212/60
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

In an approach for purging an address range from a cache, a processor quiesces a computing system. Cache logic issues a command to purge a section of a cache to higher level memory, wherein the command comprises a starting storage address and a range of storage addresses to be purged. Responsive to each cache of the computing system activating the command, cache logic ends the quiesce of the computing system. Subsequent to ending the quiesce of the computing system, Cache logic purges storage addresses from the cache, based on the command, to the higher level memory.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.