Fabrication of vertical transport fin field effect transistors with a self-aligned separator and an isolation region with an air gap
US10056289B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 20, 2017 |
| Grant date | Aug 21, 2018 |
| Priority date | — |
| Expiry date | Apr 20, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/83
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of forming a vertical transport fin field effect transistor with self-aligned dielectric separators, including, forming a bottom source/drain region on a substrate, forming at least two vertical fins on the bottom source/drain region, forming a protective spacer on the at least two vertical fins, forming a sacrificial liner on the protective spacer, forming an isolation channel in the bottom source/drain region and substrate between two of the at least two vertical fins, forming an insulating plug in the isolation channel, wherein the insulating plug has a pinch-off void within the isolation channel, and forming the dielectric separator on the insulating plug.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.