Self-aligned lithographic patterning
US10056292B2 · kind B2 · utility
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3References
20Claims
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Key dates
| Filing date | Nov 22, 2016 |
| Grant date | Aug 21, 2018 |
| Priority date | — |
| Expiry date | Nov 22, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/0337
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Methods of lithographic patterning. A metal hardmask layer is formed on a dielectric layer and a patterned layer is formed on the metal hardmask layer. A metal layer is formed on an area of the metal hardmask layer exposed by an opening in the patterned layer. After the metal layer is formed, the patterned layer is removed from the metal hardmask layer. After the patterned layer is removed, the metal hardmask layer is patterned with the metal layer masking the metal hardmask layer over the area.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.