Frank W. Mont
28Patents
4h-index
39Co-inventors
59Inventor score
Filing activity: Jan 25, 2007 → Jan 28, 2020
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US7483212B2 | Optical thin film, semiconductor light emitting device having the same and methods of fabricating the same | Physics | 37 | Active |
| US9613862B2 | Chamferless via structures | Electricity | 13 | Active |
| US9373543B1 | Forming interconnect features with reduced sidewall tapering | Electricity | 6 | Active |
| US9831174B1 | Devices and methods of forming low resistivity noble metal interconnect | Electricity | 5 | Active |
| US10032668B2 | Chamferless via structures | Electricity | 4 | Active |
| US9799555B1 | Cobalt interconnects covered by a metal cap | Electricity | 3 | Active |
| US9799559B1 | Methods employing sacrificial barrier layer for protection of vias during trench formation | Electricity | 2 | Active |
| US10056291B2 | Post spacer self-aligned cuts | Electricity | 1 | Active |
| US10157833B1 | Via and skip via structures | Electricity | 1 | Active |
| US10062560B1 | Method of cleaning semiconductor device | Electricity | 1 | Active |
| US10388565B2 | Chamferless via structures | Electricity | 1 | Active |
| US9947547B2 | Environmentally green process and composition for cobalt wet etch | Electricity | 1 | Active |
| US9831124B1 | Interconnect structures | Electricity | 1 | Active |
| US10957588B2 | Chamferless via structures | Electricity | 0 | Active |
| US10658176B2 | Methods of mitigating cobalt diffusion in contact structures and the resulting devices | Electricity | 0 | Active |
| US10636698B2 | Skip via structures | Electricity | 0 | Active |
| US10679937B2 | Devices and methods of forming low resistivity noble metal interconnect | Electricity | 0 | Active |
| US10056292B2 | Self-aligned lithographic patterning | Electricity | 0 | Active |
| US9732427B2 | Tunable nanoporous films on polymer substrates, and method for their manufacture | Emerging Cross-Sectional Technologies | 0 | Active |
| US10283608B2 | Low resistance contacts to source or drain region of transistor | Electricity | 0 | Active |
| US10262892B2 | Skip via structures | Electricity | 0 | Active |
| US11610839B2 | Dummy fill structures | Electricity | 0 | Active |
| US10636656B2 | Methods of protecting structure of integrated circuit from rework | Electricity | 0 | Active |
| US10937694B2 | Chamferless via structures | Electricity | 0 | Active |
| US11205699B2 | Epitaxial semiconductor material regions for transistor devices and methods of forming same | Electricity | 0 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.