Test structure for monitoring interface delamination
US10056306B2 · kind B2 · utility
0Cited by
0References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Feb 4, 2016 |
| Grant date | Aug 21, 2018 |
| Priority date | — |
| Expiry date | May 29, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L23/544
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Aspects of the present disclosure include a test structure that includes two or more devices. Each device includes a wire disposed within a dielectric and a first via disposed over the wire and in electrical contact with the wire. Each device includes a test pad electrically connected to the first via and a polysilicon resistor electrically connected to the wire. Each of the polysilicon resistors of the two or more devices are electrically tied together. A method for forming the interconnect structure to be used for testing is also provided.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.