Manufacuting method of semiconductor structure
US10056316B2 · kind B2 · utility
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20Claims
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Key dates
| Filing date | Nov 27, 2017 |
| Grant date | Aug 21, 2018 |
| Priority date | — |
| Expiry date | Nov 27, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10F39/809
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The present disclosure provides a semiconductor structure. The structure includes a first substrate; a first dielectric layer having a first surface in proximity to the first substrate and a second surface away from the first substrate; a first interconnect penetrating the first surface of the first dielectric layer; and a protection layer extending along a portion of a sidewall of the first interconnect. A thickness of the protection layer is in a range of from about 0.02 μm to about 0.2 μm.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.