Metal layer routing level for vertical FET SRAM and logic cell scaling
US10056377B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 17, 2017 |
| Grant date | Aug 21, 2018 |
| Priority date | — |
| Expiry date | Oct 17, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/017
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Methods of forming a VFET SRAM or logic device having a sub-fin level metal routing layer connected to a gate of one transistor pair and to the bottom S/D of another transistor pair and resulting device are provided. Embodiments include pairs of fins formed on a substrate; a bottom S/D layer patterned on the substrate around the fins; conformal liner layers formed over the substrate; a ILD formed over a liner layer; a metal routing layer formed between the pairs of fins on the liner layer between the first pair and on the bottom S/D layer between at least the second pair, an upper surface formed below the active fin portion; a GAA formed on the dielectric spacer around each fin of the first pair; and a bottom S/D contact xc or a dedicated xc formed on the metal routing layer adjacent to the GAA or through the GAA, respectively.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.