Inventor · Menands, NY, US

Steven Bentley

81Patents

17h-index

79Co-inventors

83Inventor score

Filing activity: Feb 1, 2013 → Mar 25, 2024

Most-cited inventions

Patent	Title	Area	Cited by	Status
US9530866B1	Methods of forming vertical transistor devices with self-aligned top source/drain conductive contacts	Electricity	93	Active
US9947804B1	Methods of forming nanosheet transistor with dielectric isolation of source-drain regions and related structure	Electricity	91	Active
US10192867B1	Complementary FETs with wrap around contacts and method of forming same	Electricity	82	Active
US9640636B1	Methods of forming replacement gate structures and bottom and top source/drain regions on a vertical transistor device	Electricity	66	Active
US9536793B1	Self-aligned gate-first VFETs using a gate spacer recess	Electricity	61	Active
US9773708B1	Devices and methods of forming VFET with self-aligned replacement metal gates aligned to top spacer post top source drain EPI	Electricity	57	Active
US9991352B1	Methods of forming a nano-sheet transistor device with a thicker gate stack and the resulting device	Electricity	54	Active
US10510620B1	Work function metal patterning for N-P space between active nanostructures	Electricity	54	Active
US9530863B1	Methods of forming vertical transistor devices with self-aligned replacement gate structures	Electricity	54	Active
US8716156B1	Methods of forming fins for a FinFET semiconductor device using a mandrel oxidation process	Electricity	44	Active
US10256158B1	Insulated epitaxial structures in nanosheet complementary field effect transistors	Electricity	39	Active
US9972494B1	Method and structure to control channel length in vertical FET device	Electricity	31	Active
US9825032B1	Metal layer routing level for vertical FET SRAM and logic cell scaling	Electricity	28	Active
US10236292B1	Complementary FETs with wrap around contacts and methods of forming same	Electricity	22	Active
US9165837B1	Method to form defect free replacement fins by H2 anneal	Electricity	20	Active
US9799751B1	Methods of forming a gate structure on a vertical transistor device	Electricity	19	Active
US9178036B1	Methods of forming transistor devices with different threshold voltages and the resulting products	Electricity	19	Active
US9805988B1	Method of forming semiconductor structure including suspended semiconductor layer and resulting structure	Electricity	15	Active
US10217846B1	Vertical field effect transistor formation with critical dimension control	Electricity	14	Active
US9748335B1	Method, apparatus and system for improved nanowire/nanosheet spacers	Electricity	12	Active
US10157794B1	Integrated circuit structure with stepped epitaxial region	Electricity	11	Active
US10056377B2	Metal layer routing level for vertical FET SRAM and logic cell scaling	Electricity	9	Active
US9966456B1	Methods of forming gate electrodes on a vertical transistor device	Electricity	8	Active
US11201152B2	Method, apparatus, and system for fin-over-nanosheet complementary field-effect-transistor	Electricity	8	Active
US10141414B1	Negative capacitance matching in gate electrode structures	Electricity	8	Active

Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.