Vertically stacked FinFET fuse
US10056391B2 · kind B2 · utility
4Cited by
7References
18Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jul 27, 2017 |
| Grant date | Aug 21, 2018 |
| Priority date | — |
| Expiry date | Jul 27, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/62
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor structure including a stacked FinFET fuse is provided in which the stacked FinFET fuse includes a plurality of vertically stacked and spaced apart conductive semiconductor fin portions and a doped epitaxial semiconductor material structure located on exposed surfaces of each conductive semiconductor fin portion of the vertical stack. In the FinFET fuse, a topmost surface of a bottom doped epitaxial semiconductor material structure is merged to a bottommost surface of an overlying doped epitaxial semiconductor material structure.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.