Method of improving localized wafer shape changes
US10056395B2 · kind B2 · utility
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3References
9Claims
0Family size
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Key dates
| Filing date | Oct 11, 2016 |
| Grant date | Aug 21, 2018 |
| Priority date | — |
| Expiry date | Oct 11, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D62/60
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of manufacturing an integrated circuit including forming trenches into the surface of a crystalline wafer and the trenches extending along a <100> lattice direction is disclosed. Such wafer can experience less deformation due to less stress induced when the trenches are filled using a spin-on dielectric material. Thus, the overlay issue caused by wafer shape change is resolved.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.