Semiconductor memory and method of manufacturing the same
US10056433B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 8, 2016 |
| Grant date | Aug 21, 2018 |
| Priority date | — |
| Expiry date | Aug 8, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10N70/8833
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor memory includes a plurality of stripe-like active areas formed by stacking, in a direction perpendicular to a substrate, a plurality of layers extending parallel to the substrate, a first gate electrode formed on first side surfaces of the active areas, the first side surfaces being perpendicular to the substrate, a second gate electrode formed on second side surfaces of the active areas, the second side surfaces being perpendicular to the substrate. The layers are patterned in self-alignment with each other, intersections of the active areas and the first gate electrode form a plurality of memory cells, and the plurality of memory cells in an intersecting plane share the first gate electrode.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.