Interlayer dielectric for non-planar transistors
US10056488B2 · kind B2 · utility
1Cited by
8References
11Claims
0Family size
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Key dates
| Filing date | Jan 6, 2017 |
| Grant date | Aug 21, 2018 |
| Priority date | — |
| Expiry date | Jan 6, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/76834
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The present description relates the formation of a first level interlayer dielectric material layer within a non-planar transistor, which may be formed by a spin-on coating technique followed by oxidation and annealing. The first level interlayer dielectric material layer may be substantially void free and may exert a tensile strain on the source/drain regions of the non-planar transistor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.