Single-lock delay locked loop with cycle counter and method therefore
US10056909B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | May 1, 2017 |
| Grant date | Aug 21, 2018 |
| Priority date | — |
| Expiry date | May 1, 2037 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C7/1066
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Once a delay locked loop has been locked to a clock signal, an omitted clock cycle is injected into the input of the delay locked loop without stopping the operation of the delay locked loop. The omitted cycle is later detected at an output of the delay locked loop, and the delay between the input and output is determined based on the time the omitted cycle requires to propagate through the delay locked loop. Once determined, the number of cycles of delay for the delay locked loop can be used in conjunction with an internal clock signal to launch data and/or data strobes from memory devices and memory controllers such that the proper phase alignment and clock cycle alignment is achieved.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.