Method of manufacturing a semiconductor device with multilayered channel structure
US10062782B2 · kind B2 · utility
5Cited by
15References
20Claims
0Family size
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Key dates
| Filing date | Feb 10, 2017 |
| Grant date | Aug 28, 2018 |
| Priority date | — |
| Expiry date | Feb 10, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/038
Abstract
A semiconductor device includes a fin field effect transistor (FinFET). The FinFET includes a channel disposed on a fin, a gate disposed over the channel and a source and drain. The channel includes at least two pairs of a first semiconductor layer and a second semiconductor layer formed on the first semiconductor layer. The first semiconductor layer has a different lattice constant than the second semiconductor layer. A thickness of the first semiconductor layer is three to ten times a thickness of the second semiconductor layer at least in one pair.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.