Tiled showerhead for a semiconductor chemical vapor deposition reactor
US10066297B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 27, 2015 |
| Grant date | Sep 4, 2018 |
| Priority date | — |
| Expiry date | Oct 27, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/6776
- WIPO fieldSurface technology, coating
- WIPO sectorChemistry
Abstract
A showerhead for a semiconductor processing reactor formed by an array of showerhead tiles. Each showerhead tile has a plurality of process gas apertures, which may be in a central area of the tile or may extend over the entire tile. Each showerhead tile can be dimensioned for processing a respective substrate or a plurality of substrates or the array can be dimensioned for processing a substrate. An exhaust region surrounds the process gas apertures. The exhaust region has at least one exhaust aperture, and may include an exhaust slot, a plurality of connected exhaust slots or a plurality of exhaust apertures. The exhaust region surrounds the array of showerhead tiles, or a respective portion of the exhaust region surrounds the plurality of process gas apertures in each showerhead tile or group of showerhead tiles. A gas curtain aperture may be between the exhaust region and the process gas apertures of one of the showerhead tiles or adjacent to the central area of the tile.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.