Testing holders for chip unit and die package
US10067181B2 · kind B2 · utility
3Cited by
24References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | May 12, 2017 |
| Grant date | Sep 4, 2018 |
| Priority date | — |
| Expiry date | May 12, 2037 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/2875
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A testing holder for a chip unit, a multi site holding frame for plural chip units and a method for testing a die thereof are provided. The proposed multi site holding frame for testing plural chip units simultaneously includes a first holder frame having a plurality of testing holders. Each of the plurality of testing holders includes a holder body containing a specific one of the plural chip units, and a pressure releasing device formed on the holder body to release an insertion pressure when the specific one of the plural chip units is inserted in the holder body.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.