Apparatuses, methods, and systems for memory disambiguation
US10067762B2 · kind B2 · utility
4Cited by
4References
24Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jul 1, 2016 |
| Grant date | Sep 4, 2018 |
| Priority date | — |
| Expiry date | Mar 3, 2037 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3838
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Apparatuses, methods, and systems relating to memory disambiguation are described. In one embodiment, a processor includes a decoder to decode an instruction into a decoded instruction, an execution unit to execute the decoded instruction, a retirement unit to retire an executed instruction in program order, and a memory disambiguation circuit to allocate an entry in a memory disambiguation table for a first load instruction that is to be flushed for a memory ordering violation, the entry comprising a counter value and an instruction pointer for the first load instruction.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.