Apparatuses and methods for variable latency memory operations
US10067890B2 · kind B2 · utility
7Cited by
42References
20Claims
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Key dates
| Filing date | Aug 2, 2017 |
| Grant date | Sep 4, 2018 |
| Priority date | — |
| Expiry date | Aug 2, 2037 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2207/229
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Apparatuses and methods for variable latency memory operations are disclosed herein. An example apparatus may include a memory configured to provide first information during a variable latency period indicating the memory is not available to perform a command, wherein the first information is indicative of a remaining length of the variable latency period, the remaining length is one of a relatively short, normal, or long period of time, the memory configured to provide second information in response to receiving the command after the latency period.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.