Patent · US Active

Generating clock trees for a circuit design

US10068048B1 · kind B1 · utility

5Cited by

12References

18Claims

0Family size

Assignee

XILINX, INC. · US

Inventors

Mehrdad Eslami Dehkordi · Los Gatos, US
Marvin Tom · Cupertino, US
Sridhar Krishnamurthy · San Jose, US
Frank Mueller · Wiehl, DE

Key dates

Filing date	Jul 18, 2016
Grant date	Sep 4, 2018
Priority date	—
Expiry date	Nov 25, 2036

Classification

Technology area (CPC G)Physics
CPC primaryG06F2119/12
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

The disclosure describes approaches for generating a clock tree for a circuit design. Initial clock trees are generated and elements are assigned to locations on an integrated circuit (IC). Each of the initial clock trees includes a clock root, a spine including the clock root, and branches connected to and extending from the spine. Each clock load is coupled to one of the branches. The clock tree further includes programmable delay circuits having initial delay values that are balanced. If the circuit design does not satisfy timing constraints, at least one clock root is moved from a respective first location to a respective second location.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.