Apparatuses and methods for performing multiple memory operations
US10068649B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 17, 2017 |
| Grant date | Sep 4, 2018 |
| Priority date | — |
| Expiry date | May 17, 2037 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2213/79
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The disclosed technology relates to a memory device configured to perform multiple access operations in response to a single command received through a memory controller and a method of performing the multiple access operations. In one aspect, the memory device includes a memory array comprising a plurality of memory cells and a memory controller. The memory controller is configured to receive a single command which specifies a plurality of memory access operations to be performed on the memory array. The memory controller is further configured to cause the specified plurality of memory access operations to be performed on the memory array.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.