Data structures for semiconductor die packaging
US10068786B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 20, 2017 |
| Grant date | Sep 4, 2018 |
| Priority date | — |
| Expiry date | Apr 20, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2223/54486
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
At least some embodiments are directed to a system that comprises storage comprising a data structure that cross-references an identifier of a semiconductor wafer, a location of a die in the wafer, an identifier of a lead frame strip, a location of a lead frame in the lead frame strip, and results of a first test on the die. The system also comprises mechanical equipment configured to test packaged die. The system further comprises a processor, coupled to the storage and to the mechanical equipment, configured to perform a second test on a package containing the die and the lead frame using the mechanical equipment and the results of the first test.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.