Method of reducing charge loss in non-volatile memories
US10068912B1 · kind B1 · utility
3Cited by
7References
20Claims
0Family size
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Key dates
| Filing date | Jun 5, 2017 |
| Grant date | Sep 4, 2018 |
| Priority date | — |
| Expiry date | Jun 5, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/037
Abstract
A memory apparatus that has at least two non-volatile memory (NVM) cells disposed side by side overlying a substrate and an isolation structure disposed between the first and second NVM cells in the substrate. The first and second NVM cells share a common charge trapping layer that includes a continuous structure, and the portion of the common charge trapping layer that is disposed directly above the isolation structure includes a higher oxygen and/or nitrogen concentration than the portions of the common charge trapping layer that are disposed within the first and second NVM cells.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.