Patent · US Active

Erase for partially programmed blocks in non-volatile memory

US10074440B2 · kind B2 · utility

3Cited by
38References
17Claims
0Family size

Assignee

Inventors

Key dates

Filing dateOct 28, 2016
Grant dateSep 11, 2018
Priority date
Expiry dateNov 3, 2036

Classification

  • Technology area (CPC G)Physics
  • CPC primaryG11C16/3459
  • WIPO fieldComputer technology
  • WIPO sectorElectrical engineering

Abstract

An erase operation includes one or more erase depth checks to detect the occurrence of shallow erased memory cells at the end of an erase process. Memory cells are subjected to erase and erase verification until erase verification success is achieved. At the end of successful erase verification, a subset of memory cells is read to detect an erase depth or level of the memory cells. If the erase depth check indicates that the subset memory cells are in a shallow erased condition, additional erasing and verification is performed.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.