High dry etch rate materials for semiconductor patterning applications
US10074543B2 · kind B2 · utility
22Cited by
114References
26Claims
0Family size
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Key dates
| Filing date | Aug 31, 2016 |
| Grant date | Sep 11, 2018 |
| Priority date | — |
| Expiry date | Aug 31, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B12/01
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Methods and apparatuses for depositing low density spacers using atomic layer deposition for negative patterning schemes are provided herein. Methods involve one or more of: (1) exposing a substrate to a plasma for a duration less than about 300 ms in each cycle of alternating pulses of a deposition precursor and oxidizing plasma; (2) exposing the substrate to the plasma at a radio frequency power density of less than about 0.2 W/cm2; and (3) exposing the substrate to the plasma produced from a process gas having an argon to oxidant ratio of at least about 1:12.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.