Integrating and isolating nFET and pFET nanosheet transistors on a substrate
US10074575B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 21, 2017 |
| Grant date | Sep 11, 2018 |
| Priority date | — |
| Expiry date | Jun 21, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/0262
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Embodiments of the invention are directed to methods of fabricating nanosheet channel field effect transistors. An example method includes forming a first sacrificial nanosheet and forming a first nanosheet stack over the first sacrificial nanosheet, wherein the first nanosheet stack includes alternating channel nanosheets and sacrificial nano sheets. The method further includes exposing a surface area of the first sacrificial nanosheet and exposing surface areas of the alternating channel nanosheets and sacrificial nanosheets, wherein the exposed surface area of the first sacrificial nanosheet is greater than each of the exposed surface areas of the alternating channel nanosheets and sacrificial nanosheets. The method further includes applying an etchant to the exposed surface areas, wherein the etchant is selective based at least in part on the amount of surface area to which the etchant is applied.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.