Inventor · Niskayuna, NY, US

Muthumanickam Sankarapandian

77Patents
9h-index
130Co-inventors
81Inventor score

Filing activity: Nov 5, 2002 → Nov 10, 2021

Most-cited inventions

PatentTitleAreaCited byStatus
US7855101B2 Layer transfer process and functionally enhanced integrated circuits produced thereby Electricity 299 Active
US6911400B2 Nonlithographic method to produce self-aligned mask, articles produced by same and compositions for same Emerging Cross-Sectional Technologies 58 Expired
US10074575B1 Integrating and isolating nFET and pFET nanosheet transistors on a substrate Electricity 35 Active
US8927442B1 SiCOH hardmask with graded transition layers Electricity 24 Active
US8916337B2 Dual hard mask lithography process Emerging Cross-Sectional Technologies 20 Active
US6641899B1 Nonlithographic method to produce masks by selective reaction, articles produced, and composition for same Emerging Cross-Sectional Technologies 20 Expired
US8859433B2 DSA grapho-epitaxy process with etch stop material Electricity 19 Active
US9171927B2 Spacer replacement for replacement metal gate semiconductor devices Electricity 9 Active
US10256320B1 Vertical field-effect-transistors having a silicon oxide layer with controlled thickness Electricity 9 Active
US7781332B2 Methods to mitigate plasma damage in organosilicate dielectrics using a protective sidewall spacer Electricity 8 Active
US8470706B2 Methods to mitigate plasma damage in organosilicate dielectrics Electricity 7 Active
US7750479B2 Treatment of plasma damaged layer for critical dimension retention, pore sealing and repair Electricity 7 Active
US8835326B2 Titanium-nitride removal Electricity 6 Active
US8481423B2 Methods to mitigate plasma damage in organosilicate dielectrics Electricity 6 Active
US7378738B2 Method for producing self-aligned mask, articles produced by same and composition for same Emerging Cross-Sectional Technologies 6 Expired
US10242920B2 Integrating and isolating NFET and PFET nanosheet transistors on a substrate Electricity 6 Active
US10374034B1 Undercut control in isotropic wet etch processes Electricity 5 Active
US8129843B2 Methods to mitigate plasma damage in organosilicate dielectrics using a protective sidewall spacer Electricity 5 Active
US7830010B2 Surface treatment for selective metal cap applications Electricity 5 Active
US10475904B2 Methods of forming merged source/drain regions on integrated circuit products Electricity 4 Active
US8491987B2 Selectively coated self-aligned mask Emerging Cross-Sectional Technologies 4 Active
US10304936B2 Protection of high-K dielectric during reliability anneal on nanosheet structures Electricity 4 Active
US10396208B2 Vertical transistors with improved top source/drain junctions Electricity 4 Active
US11171051B1 Contacts and liners having multi-segmented protective caps Electricity 4 Active
US7459183B2 Method of forming low-K interlevel dielectric layers and structures Electricity 4 Active

Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.